Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog hdl code

Search list

[VHDL-FPGA-Verilog] trafficlight_design_based_on_fpga

Description: 基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize
Platform: | Size: 408576 | Author: | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[SCM] seg7led

Description: Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through
Platform: | Size: 113664 | Author: 刘洪国 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] ffcsr

Description: 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 2048 | Author: 李辛 | Hits:

[Speech/Voice recognition/combine] speech

Description: 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
Platform: | Size: 3072 | Author: ji | Hits:

[VHDL-FPGA-Verilog] fftshixian

Description: OFDM系统中FFT的Verilog HDL 语言实现。-OFDM system FFT of Verilog HDL language.
Platform: | Size: 14512128 | Author: 江金华 | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] verilog_hdl

Description: 精通verilog_hdl语言编程实例程序代码，基于verilog硬件语言的程序设计实例，主要是数字电路方面-Verilog_hdl proficient in language programming examples of program code, based on the Verilog hardware design language of the procedure, the main aspects of digital circuit
Platform: | Size: 49152 | Author: songjunmin | Hits:

[Communication-Mobile] ldpc

Description: 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
Platform: | Size: 9216 | Author: fly | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[VHDL-FPGA-Verilog] Microprocessor

Description: 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
Platform: | Size: 774144 | Author: 孟霑 | Hits:

[VHDL-FPGA-Verilog] HDLcodingstyle

Description: verilog HDL 代码综合风格，非常适合初学者-verilog HDL code integrated style, very suitable for beginners
Platform: | Size: 1680384 | Author: 许伟 | Hits:

[VHDL-FPGA-Verilog] beipin_top

Description: 次代码利用verilog HDL来描述的，可以实现2倍频功能，只是频率有一点误差。-Times verilog HDL code to describe the use of, 2 octave function can be achieved, but the frequency of a bit error.
Platform: | Size: 101376 | Author: 刘三平 | Hits:

[Special Effects] H264

Description: h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
Platform: | Size: 99328 | Author: 陈成 | Hits:

[VHDL-FPGA-Verilog] sdramc_controller

Description: 基于verilog hdl的SDRAM控制代码-SDRAM-based control of the verilog hdl code
Platform: | Size: 6144 | Author: wxd | Hits:

[VHDL-FPGA-Verilog] 4NandFlash

Description: 基于verilog hdl 的Nand Flash控制代码-Verilog hdl-based control code of the Nand Flash
Platform: | Size: 2048 | Author: wxd | Hits:
« 1 2 3 4 5 6 7 89 10 11 12 13 ... 27 »

CodeBus www.codebus.net